- By: Ken Gracey Published: 19 September, 2014 3 comments
The last time we provided a schedule update for Propeller 2 was in February, 2014. That schedule had us in the foundry this month with samples arriving by the end of October. Today it’s nearly October and we’re nowhere near being ready to submit any design files for fabrication!
The drawback of our transparency about an upcoming product is that all of us must be willing to accept the research and design cycle that accompanies a small company that decides to design its own chip. But we think the benefits are much bigger: early FPGA releases, the open source Propeller 1, and early details to design the Propeller 2 into your project before it is available. This is your chip as much as it is ours.
Propeller 2 Multicore Specifications
Let’s take a look at the Propeller 2 specifications as they’re shaping up:
- 200 Mhz clock, 16 cogs, 100 MIPS per cog, for 1600 total MIPS
- 512KB hub memory with each cog having an independent 800 MB/s port to hub memory
- Cogs can execute code from both cog memory and hub memory
- 32-bit pipelined CORDIC solver shared by all cogs (SIN/COS/ATAN/LOG/EXP)
- Software-configurable ADC, DAC, and digital on every I/O pin
- Possibility of large data/program storage through external SDRAM
- 64 I/Os in thermal-pad 100-pin TQFP package
These specifications may change as we continue with the design.
I asked Chip for some details on his workflow to understand the steps to complete the Propeller 2. He’s been working through the nights and feeling positive about his progress, reporting the following:
“I’m revisiting the I/O pins that make up the pad frame and I’m optimizing them for the ONC18 process. I didn’t expect to take the plunge down this mine shaft, but the ADC is being greatly improved. When I get back to the surface, I’ll resume work on the Verilog code which will yield some FPGA updates for our interested customers. The next steps will be to do the synthesis and integration of the manual layout.”
There is no date. This is taking longer than we thought. Our best estimate is that customers could hope for an FPGA image by Christmas. In the meantime, we’ll be taking a closer look at the open source Propeller 1.5 Verilog improvements made by our customers.
My experience working with Chip is that his projects become complex before they become simple. Several iterations often lead to the final design which is smaller, more efficient and simpler than originally envisioned. There won’t be any buggy silicon from Parallax and we expect it’ll be worth the wait.
- Ken Gracey, CEO