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Parallax Insider News

Propeller 2 Schedule Update: The longer we work, the simpler our new multicore design will become

  • By: Ken Gracey Published: 19 September, 2014 3 comments

The last time we provided a schedule update for Propeller 2 was in February, 2014. That schedule had us in the foundry this month with samples arriving by the end of October. Today it’s nearly October and we’re nowhere near being ready to submit any design files for fabrication!

The drawback of our transparency about an upcoming product is that all of us must be willing to accept the research and design cycle that accompanies a small company that decides to design its own chip. But we think the benefits are much bigger: early FPGA releases, the open source Propeller 1, and early details to design the Propeller 2 into your project before it is available. This is your chip as much as it is ours.

Propeller 2 Multicore Specifications

Let’s take a look at the Propeller 2 specifications as they’re shaping up:

  • 200 Mhz clock, 16 cogs, 100 MIPS per cog, for 1600 total MIPS
  • 512KB hub memory with each cog having an independent 800 MB/s port to hub memory
  • Cogs can execute code from both cog memory and hub memory 
  • 32-bit pipelined CORDIC solver shared by all cogs (SIN/COS/ATAN/LOG/EXP)
  • Software-configurable ADC, DAC, and digital on every I/O pin
  • Possibility of large data/program storage through external SDRAM
  • 64 I/Os in thermal-pad 100-pin TQFP package

These specifications may change as we continue with the design.

Development Cycle

I asked Chip for some details on his workflow to understand the steps to complete the Propeller 2. He’s been working through the nights and feeling positive about his progress, reporting the following:

“I’m revisiting the I/O pins that make up the pad frame and I’m optimizing them for the ONC18 process. I didn’t expect to take the plunge down this mine shaft, but the ADC is being greatly improved. When I get back to the surface, I’ll resume work on the Verilog code which will yield some FPGA updates for our interested customers. The next steps will be to do the synthesis and integration of the manual layout.”

The Date

There is no date. This is taking longer than we thought. Our best estimate is that customers could hope for an FPGA image by Christmas. In the meantime, we’ll be taking a closer look at the open source Propeller 1.5 Verilog improvements made by our customers.

My experience working with Chip is that his projects become complex before they become simple. Several iterations often lead to the final design which is smaller, more efficient and simpler than originally envisioned. There won’t be any buggy silicon from Parallax and we expect it’ll be worth the wait.

- Ken Gracey, CEO

Comments

YABADABADOO!!!
Many many greetings the Genius Chip Gracey

Francesco Santandrea
from Rome - Italy

It will be worth the wait, I have no doubt.

This is, in a large part, the nature of being a small, growing organisation with innovative products and ideas and normal resource constraints, no clones of Chip or Ken! All organisations that are growing and innovate go through it at some point and the pressure can be intense.

This very thing though, like a boxer "punching above his weight" adds very real interest and value to Parallax products.

A quote attributed to Shigeru Miyamoto, well known game designer at Nintendo, says it quite well and I think it can be just as applicable in the silicon business (with the word "processor" substituted for "game" of course). In case you haven't seen it somewhere, it is, "A delayed game is eventually good, a bad game is bad forever." In my experience this is just as applicable to silicon and other complex design and development tasks as it is to games and to software in general. Perhaps more so in some ways! Remediation of a silicon product with a bug, particularly a bug that is not intuitivly obvious is very difficult. Software can go to the next release.

It is in the end a creative process that is happening not "just" engineering and while I am sure that you (Chip and Ken and perhaps all of Parallax) will be glad when it is debugged, tested and shipping, we know it takes time to get it right and iteration over the design is necessary. The latter is true, even with the very large scale R&D funding available, abundant tools and hundreds of skilled personnel.

Dear Sir,

It will indeed be worth the wait. Im very excited about getting my hands on this. The ADC and enhanced features make it ideal and competitive. Can't wait!!

Keep up the great work!!!

Sincerely John
Down under